1. Technical Field
The present invention relates to a test module, a test apparatus, and a test method. In particular, the present invention relates to a test module, a test apparatus, and a test method for performing phase correction, with respect to an input signal, on an output signal from an output terminal of a device under test.
2. Related Art
A test apparatus tests a device under test (DUT), which is a test target, based on a test program. The test program includes, for each command cycle, commands to be executed by the test apparatus and expected value patterns to be compared with a test pattern output to each terminal of the device under test or an output pattern output from each terminal of the device under test.
It is possible that, with the device under test, the number of cycles from when a test pattern is input to when an output pattern corresponding to this test pattern is output is unknown or inconsistent. When comparing the output patterns output by such a device under test to expected value patterns, the test apparatus preferably has a function, e.g. a hunt function, to detect the output of a predetermined header pattern from the device under test and to compare an expected value pattern to a target output pattern that is output a specified number of cycles after the header pattern.
For example, Patent Document 1 discloses a test apparatus and a test method for synchronizing the output of an output pattern sequence with the reading of an expected value pattern sequence in order to perform the comparison. This test apparatus includes a header pattern detecting section that, when a detection start command ordering the start of a search for the pattern header sequence is executed, detects whether the pattern header pattern is output from the device under test, and a timing adjusting section that, when the pattern header sequence is detected, synchronizes the expected value pattern and the output pattern to input both patterns to an expected value comparing section in the same cycle.
Patent Document 1: Japanese Patent Application Publication No. 2006-10651
Conventionally, in order to obtain a phase shift of the DUT output, which is the goal of the hunt function, the header pattern is supplied to the DUT, the output patterns from the DUT are accumulated, and a prescribed pattern corresponding to the header pattern is detected. Here, the amount of output patterns accumulated from the DUT must be at least equal to the length of the header pattern and a hunt delay amount is added to sufficiently exceed the necessary phase shift amount. When performing match detection simultaneously for all bits resulting from the hunt delay added to the length of the header pattern, if the hunt delay is large, the number of match detection circuits provided in parallel increases, thereby increasing circuit size.